View MSM6562B_4358.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

E2B0035-27-Y3
Semiconductor MSM6562B-xx
Semiconductor DOT MATRIX LCD CONTROLLER DRIVER
This version: Nov. 1997 MSM6562B-xx Previous version: Mar. 1996
GENERAL DESCRIPTION
The MSM6562B-xx controls a character type dot matrix LCD in combination with an 8-bit or 4bit microcontroller. The MSM6562B-xx can control a display of up to 40 characters. With the display data serial transfer function, the MSM6562B-xx, when used in combination with the character extension IC (MSM5259), can control a maximum of 80 characters.
FEATURES
* * * * * * * * * * * * * Easy interface with an 8-bit or 4-bit microcontroller. Dot matrix LCD controller driver for 5 7 dots font or 5 10 dots font. Automatic power ON reset. 16 COMMON signal drivers and 100 SEGMENT signal drivers are built in. Can control up to 80 characters when used in combination with MSM5259. Built-in character generator ROM for 160 characters with 5 7 dots font and 32 characters with 5 10 dots font. Character patterns can be programmed by CG RAM. (5 8 dots font: 8 kinds, 5 11 dots font: 4 kinds) 1/8 duty (1 line; 5 7 dots + cursor), 1/11 duty (1 line; 5 10 dots + cursor), or 1/16 duty (2 lines; 5 7 dots + cursor) selectable. Built-in RC oscillation circuit by an external resistor or an internal resistor. Built-in bias dividing resistors for LCD driving. Built-in contrast adjusting circuit. Bidirectional transfer available on segment output. Aluminum pad chip (Product name: MSM6562B-xx) xx indicates code number.
1/50
BLOCK DIAGRAM
Semiconductor
VDD VSS OSC1 OSCR OSC2 Timing generation circuit
L CP DF
7
Cursor blink control 8 Instruction decoder (ID) 7
16-bit 16 COMMON 16 signal shift driver register Parallel/ serial conversion
E R/W RS0 RS1 DB0 - DB3 4
COM1 - 16
8
Instruction register (IR)
Input/ output buffer 8 Data register (DR) 8
Character generator RAM (CG RAM) 8
5
5
Character generator ROM (CG ROM)
DB4 - DB7
4
SEGMENT signal driver
100-bit shift register
100-bit latch
100
100
100
T1 T2 T3 V1 V2 V3' V3 V4 V5 V5'
Test circuit
LCD bias voltage dividing circuit
Busy flag (BF) 5 5 Contrast register (CR)
Address counter (ADC)
SEG1 - 100
8 7 Display data RAM (DD RAM)
MSM6562B-xx
DO SHL1 SHL0
2/50
Semiconductor
MSM6562B-xx
INPUT AND OUTPUT CONFIGURATION
VDD VDD P VDD P VDD P
N
N
N
Applied to Pin E. VDD
Applied to Pins T1, T2 and T3.
Applied to Pins R/W, RS0 and RS1.
VDD P VDD P
N VDD P
N
N
Applied to DO, CP, L and DF.
Applied to DB0 - DB7.
3/50
Semiconductor
MSM6562B-xx
PIN DESCRIPTIONS
Symbol R/W RS0, RS1 E DB0 - DB7 OSC1, OSC2, OSCR Read/write selection input pin. "H": Read, and "L": Write Register selection input pins.
RS0 "H" RS1 "H": Data register RS0 "L" RS1 "H" : Instruction register RS0 "L" RS1 "L" : Contrast register
Description
Input pin for data input/output between CPU and MSM6562B-xx and for activating instruction. Input/output pins for data send/receive between CPU and MSM6562B-xx. Clock oscillating pins required for internal operation upon receipt of CPU instruction and the LCD drive signal. When oscillated by an external resistor, connect a resistor between OSC1 and OSC2. When oscillated by a built-in resistor, connect OSCR and OSC2 externally.
COM1 - COM16 SEG1 - SEG100 SHL0, SHL1 DO CP L DF VDD VSS V1 - V5, V3'
LCD COMMON signal output pins. LCD SEGMENT signal output pins. Input pins to control the transfer direction of the SEGMENT signal output data. See table below. Data output pin to send serial data to the character extension IC. Clock output pin to transfer the serial data to the character extension IC. Latch output pin to latch the transferred data to the character extension IC. Output pin for the alternating signal (DF, display frequency) required for an LCD display. Power supply pin. Ground pin. Bias voltage input pins to drive an LCD and bias setting pin. (Built-in bias dividing resistor) 1/4 bias : Connect V2 and V3. Leave V3' open. 1/5 bias : Connect V3 and V3'. Since VLCD value depends on V5 voltage, connect a variable resistor between V5 pin and VSS potential or connect V5 pin and V5' pin to adjust VLCD.
V5'
Contrast adjusting voltage output pin.
SHL0 L L H H
SHL1 L H L H
Segment data transfer direction SEG1AESEG100 SEG100AESEG1 SEG1AESEG50fiSEG100AESEG51 SEG100AESEG1
4/50
Semiconductor
MSM6562B-xx
ABSOLUTE MAXIMUM RATINGS
Parameter Supply voltage Supply voltage for LCD display Input voltage Symbol VDD V1, V2, V3, V4, V5 VI Condition Ta = 25C Ta = 25C Rating -0.3 to + 7.0 -0.3 to VDD + 0.3 Unit V V
Applicable Pin
VDD, VSS V1, V2, V3, V4, V5 R / W, RS1, RS0, E, DB0 - DB7 OSC1 -- --
Ta = 25C
-0.3 to VDD + 0.3
V
Junction temperature Storage temperature
Tj TSTG
-- --
150 -55 to + 150
C C
RECOMMENDED OPERATING CONDITIONS
Parameter Supply voltage LCD driving voltage Operating temperature Symbol VDD VLCD Top Condition -- VDD - VSS 1/4 bias *1 VDD - VSS 1/5 bias *2 -- Range 4.5 to 5.5 3.0 to 5.5 *3 3.0 to 5.5 *3 -30 to +85 Unit V V V C
Applicable Pin
VDD, VSS VDD, V5 --
*1
This voltage should be applied to VDD - V5. Voltages applicable to V1, V2, V3 and V4 are as follows: V1 = VDD - 1/4 (VDD - V5) V2 = V3 = VDD - 1/2 (VDD - V5) V4 = VDD - 3/4 (VDD - V5) This voltage should be applied to VDD - V5. Voltages applicable to V1, V2, V3 and V4 are as follows: V1 = VDD - 1/5 (VDD - V5) V2 = VDD - 2/5 (VDD - V5) V3 = VDD - 3/5 (VDD - V5) V4 = VDD - 4/5 (VDD - V5) The relation of VDD > V1 > V2 V3 (=V3') > V4 > V5 VSS must be kept. (High AE Low) LCD driving voltage can be adjusted by varying V5. However, V5 cannot be used under VSS voltage.
*2
*3
5/50
Semiconductor
MSM6562B-xx
ELECTRICAL CHARACTERISTICS DC Characteristics
(VDD = 4.5 to 5.5V, Ta = -30 to +85C) Parameter "H" input voltage "L" input voltage "H" input voltage "L" input voltage "H" output voltage "L" output voltage "H" output voltage "L" output voltage COM voltage drop SEG voltage drop Input leakage current Symbol VIH1 VIL1 VIH2 VIL2 VOH1 VOL1 VOH2 VOL2 VC VS IIL Condition -- -- -- -- IO = -0.205mA IO = 1.6mA IO = -40mA IO = 40mA IO = 40mA (Note 1) IO = 40mA (Note 1) VI = VDD VI = VSS
VI = VDD Except the current flowing to the pull-up resistor and output driving MOS.
Min. 2.2 -0.3 VDD - 0.8 -0.3 2.4 -- 0.9VDD -- -- -- -- -- --
Typ. -- -- -- -- -- -- -- -- -- -- -- -- --
Max. VDD 0.6 VDD 0.8 -- 0.4 -- 0.1VDD 2.3 3.0 1 -1 2
Unit V V V V V V V V V V mA mA mA
Applied Pin R/W, RS0, RS1, E, DB0 - DB7 OSC1 SHL0, SHL1 DB0 - DB7 DO, CP, L, DF, OSC2 COM1 - COM16 SEG1 - SEG100 E, SHL0, SHL1
"H" input current
IIH2
R/W, RS0, RS1, DB0 - DB7
"L" input current
IIL2
VDD = 5.0V VI = VSS
VDD = 5.0V E = "L" level, SHL0, SHL1 = "L" level Built-in Rf oscillation or external clock input to OSC1. External clock frequency (fIN) is 270kHz. R/W, RS0, RS1, and DB0 to DB7 are open. Output pins are all no load. Except bias current for LCD driving. (Note 2, 3, 4)
-34
-83
-204
mA
Supply current
IDD
--
--
1
mA
VDD
LCD driving bias resistance
LBR
--
2
4
8
kW
VDD - V1, V1 - V2 V2 - V3', V3 - V4 V4 - V5
Variable range by built-in VLCD MAX variable resistor for LCD driving voltage VLCD MIN LCD driving bias voltage (external input) VLCD1 VLCD2
VDD = 5.0V, 1/5 bias VDD = 5.0V, 1/5 bias VDD - V5 (Note 5) 1/5 bias 1/4 bias
4.6 -- 3.0 3.0
-- -- -- --
-- V 3.7 5.5 V 5.5
VDD, V1, V2, V3, V3', V4, V5
VDD - V5 (V5')
6/50
Semiconductor
MSM6562B-xx
(Note
1)
Applies to the voltage drop (VC) from VDD, V1, V4 and V5 to each COMMON pin (COM1 to COM16) as well as to voltage drop (VS) from VDD, V2, V3 and V5 to each SEG pin (SEG1 to SEG100) when 40mA is flowed through one COM or SEG pin. When output level is at VDD, V1, or V2 level, 40mA is flowed out, while 40mA is flowed in when the output level is at V3, V4 or V5 level. This occurs when 5V is input to VDD, V1 and V2 , and 0V is input to V3, V4 and V5.
(Note
2)
Applies to the current value flowed in the pin VDD, in the case of VDD = 5V, VSS = 0V, V1, V2 = 5V, V3, V4, V5 = 0V and V5' is open. Built-in Rf oscillation circuit
OSC1 OSCR OSC2
Minimum wiring is required between OSCR and OSC2. Leave OSC1 open.
(Note
3)
(Note
4)
External clock input circuit
Input pulse
OSC1 OSCR OSC2
Leave OSCR and OSC2 open.
(Note
5) Input the voltage to V5. (However, V5 cannot be used under VSS voltage.)
N (number of LCD lines)
Pin V1 V2 V3 V4 V5
1-line mode Bias : 1/4 VDD - VDD - VDD - VDD - VLCD 4 VLCD 2 VLCD 2
2-line mode Bias : 1/5 VDD - VDD - VDD - VDD - VLCD 5
2VLCD 5 3VLCD 5 4VLCD 5
3VLCD 4
VDD - VLCD
VDD - VLCD
At 1/4 bias : Connect V2 and V3 externally and leave V3' open. At 1/5 bias : Connect V3 and V3' externally. VLCD is the LCD driving voltage. (For N [number of LCD lines], refer to the explanation of the Function setting instruction of the instruction code.) 7/50
Semiconductor
MSM6562B-xx
AC Characteristics
Parameter Rf clock oscillation frequency External clock frequency Symbol fOSC1 Condition Rf = 120 kW 2% (Note 1) OSCR and OSC2 are open. Input a pulse to OSC1. (Note 4) (Note 2) (Note 3) (Note 3) OSC1 is open. (Note 5) Connect OSCR and OSC2. Min. 175 Typ. 270 Max. 350 Unit Applicable Pin kHz OSC1 OSC2
fIN
125
--
480
kHz
OSC1
External clock duty External clock rise time External clock fall time Built-in Rf clock oscillation frequency
fduty trf tff
45 -- --
50 -- --
55 0.2 0.2
% ms ms
OSC1 OSC1 OSC1 OSC1 OSCR OSC2
fOSC2
140
280
480
kHz
(Note
1)
OSC1 OSCR OSC2
Rf = 120kW 2% Rf Minimum wiring is required between OSC1 and Rf and between OSC2 and Rf. Leave OSCR open.
(Note
2)
tHW tLW Applies to the pulse to be input to OSC1 VDD 2 VDD 2 VDD 2
fIN waveform
fduty = tHW /(tHW + tLW) 100 (%)
(Note
3)
Applies to the pulse to be input to OSC1.
Applies to the pulse to be input to OSC1 VDD - 0.8V VDD - 0.8V 0.8V
fIN waveform
0.8V
(Note (Note
4) 5)
trf tff See Note 4 to "DC Characteristics."
See Note 3 to "DC Characteristics."
8/50
Semiconductor
MSM6562B-xx
Switching Characteristics
1. Timing for input from the CPU (write operation)
(VDD = 4.5 to 5.5V, Ta = -30 to +85C) Parameter R/W, RS0 and RS1 setup time E "H" pulse width R/W, RS0 and RS1 hold time E rise time E fall time E "L" pulse width E cycle time DB0 to DB7 input data setup time DB0 to DB7 input data hold time Symbol Min. 40 220 10 -- -- 210 500 100 10 Typ. -- -- -- -- -- -- -- -- -- Max. -- -- -- 20 20 -- -- -- -- Unit ns ns ns ns ns ns ns ns ns
tB tW tA tr tf tL tC tI tH
RS1, 0
VIH1 VIL1
VIH1 VIL1
R/W
VIL1 tB tL tr VIH1 VIL1 tI tW tf VIH1 VIL1 tH
VIL1 tA
E
VIL1
DB0-7 tc
VIH1 Input data VIL1
VIH1 VIL1
9/50
Semiconductor 2. Timing for output to the CPU (read operation)
MSM6562B-xx
(VDD = 4.5 to 5.5V, Ta = -30 to +85C) Parameter R/W, RS0 and RS1 setup time E "H" pulse width R/W, RS0 and RS1 hold time E rise time E fall time E "L" pulse width E cycle time DB0 to DB7 data ouput delay time DB0 to DB7 data ouput hold time Symbol Min. 40 220 10 -- -- 210 500 -- 20 Typ. -- -- -- -- -- -- -- -- -- Max. -- -- -- 20 20 -- -- 150 -- Unit ns ns ns ns ns ns ns ns ns
tB tW tA tr tf tL tC tD tO
RS1, 0
VIH1 VIL1
VIH1 VIL1
R/W
VIL1 tB tL tr VIL1 VIL1 tD tW tf VIH1 VIL1 tO VOH1 Output data VOL1 tc
VIL1 tA
E
VIL1
DB0-7
VOH1 VOL1
10/50
Semiconductor 3. Timing for output to character extension IC
MSM6562B-xx
(VDD = 4.5 to 5.5V, Ta = -30 to +85C) Parameter CP "H" pulse width CP "L" pulse width DO setup time DO hold time L clock setup time L clock hold time L "H" pulse width DF delay time Symbol Min. 800 800 300 300 500 100 800 -1000 Typ. -- -- -- -- -- -- -- -- Max. -- -- -- -- -- -- -- 1000 Unit ns ns ns ns ns ns ns ns
tHW1 tLW tS tDH tSU tHO tHW2 tM
DO tHW1 CP VOH2 VOH2 VOL2 tLW
VOH2 VOL2 tS VOH2 VOL2
VOH2 VOH2 tDH VOH2 VOL2 tSU tHO VOH2 VOL2 tM VOH2
L
VOH2 tHW2
DF
11/50
Semiconductor
MSM6562B-xx
FUNCTIONAL DESCRIPTION
1. Instruction Register (IR), Data Register (DR), Contrast Register (CR) These three registers are selected by the register selector pins, RS0 and RS1. When RS0 and RS1 are "H" level input, the DR is selected and when RS0 = "L" level input and RS1 = "H", the IR is selected. On the other hand, when RS0 and RS1 are "L" level input, the CR is selected. (When RS0 = "H" level input and RS1 = "L", the registers are ignored.) The IR is used to store the address codes for the display data RAM (DD RAM) or character generator RAM (CG RAM) and instruction codes. The IR can be written into, but not be read out by the microcomputer (CPU). The CR can be used to read out and write. The CR values provide 0 to 1F (hexadecimal) and when this value is 0, VLCD is lowest. On the other hand, when it is 1F, it is highest. (The initial value is 1F.) Therefore, the contrast can be adjusted by varying the CR value (providing that V5 and V5' are connected). The DR is used to write into/read out the data to/from the DD RAM or CG RAM. The data written to the DR by the CPU is automatically written to the DD RAM or CG RAM as an internal operation. When an address code is written to the IR, the data (of the specified address) is automatically transferred from the DD RAM or CG RAM to the DR. By having the CPU subsequently read the DR (from the DR data), it is possible to verify the DD RAM or CG RAM data. After the writing of the DR by the CPU, the DD RAM or CG RAM of the next address is selected to be ready for the next CPU writing. Likewise, after the reading out of the DR by the CPU, the DD RAM or CG RAM data is read out by the DR to be ready for the next CPU reading. Write/read to and from the three registers is carried out by the READ/WRITE (R/W) pin.
Table 1
R/W L H L H L H RS0 L L H H L L RS1 H H H H L L
Register and R/W pins function table
Function IR write Read of busy flag (BF) and address counter (ADC) DR write DR read CR write CR read
2. Busy Flag (BF) When the busy flag output is at "H", it indicates that the MSM6562B-xx is engaged in internal operation. When the busy flag is at "H" level, any new instruction is ignored. When R/W = "H", RS0 = "L", and RS1 = "H", the busy flag is output from DB7. New instruction should be input when BF is "L" level. When the busy flag is set to "H", the output code of the address counter (ADC) are undefined.
12/50
Semiconductor 3. Address Counter (ADC)
MSM6562B-xx
The address counter (ADC) allocates the address for the DD RAM and CG RAM and also for the cursor display. When the instruction code for the DD RAM address or CG RAM address setting is input to the IR, after deciding whether it is the DD RAM or CG RAM, the address code is transferred from the IR to the ADC. After writing (reading) the display data to (from) the DD RAM or CG RAM, the ADC is automatically incremented (decremented) by 1 as its internal operation. The data of the ADC is output to DB0 - DB6 under the conditions that R/W = "H", RS0 = "L", RS1 = "H" and BF = "L".
4. Timing Generator Circuit This circuit generates timing signals used for internal operations upon receipt of CPU instruction. It also generates timing signals for activating such internal circuits as the DD RAM, CG RAM and CG ROM. It is so designed that the internal operation caused by accessing from the CPU will not interfere with the internal operation caused by the LCD display. Consequently, when data is written from the CPU to DD RAM no ill effect, e.g., flickering occurs in portions other than the display where the data is written. In addition, the circuit generates transfer signals to the character extension IC (MSM5259).
13/50
Semiconductor 5. Display Data RAM (DD RAM)
MSM6562B-xx
This RAM is used to store the display data of 8-bit character codes (see Table 2). DD RAM address corresponds to the display position of the LCD. The correspondence between the two is described in the following.
DD RAM address (set to ADC) is expressed in hexadecimal notation as shown below: DB6 ADC MSB DB0 LSB
Hexadecimal notation
Hexadecimal notation
(Example) When DD RAM address is 2A
L
H
L
H
L
H
L
2
A
1-1)
Correspondence between address and display position in the 1-line display mode
2 01 3 02 4 03 5 04 79 4E 80 4F LSB Display position DD RAM address (hex.)
First digit 00 MSB
1-2)
When the MSM6562B-xx alone is used, up to 20 characters can be displayed from the first digit to the twentieth digit.
2 01 3 02 4 03 19 12 20 13
First digit 00
display
When the display is shifted by instruction, the correspondence between the LCD position and the DD RAM address changes as shown below:
First digit 2 00 2 02 3 01 3 03 4 02 4 04 19 11 19 13 20 12 20 14
(Display shifted to right)
4F
First digit (Display shifted to left) 01
14/50
Semiconductor 1-3)
MSM6562B-xx
When the MSM6562B-xx is used with one MSM5259, up to 28 characters can be displayed from the first digit to the twenty-eighth digit as shown below:
2 01 3 02 4 03 19 12 20 13 21 14 22 15 23 16 24 17 25 18 26 19 27 1A 28 1B
First digit 00
MSM6562B-xx display
MSM5259 display
When the display is shifted by instruction, the correspondence between the LCD display and DD RAM address changes as shown below:
First digit 2 (Display shifted to right) 4F 00 3 01 4 02 19 11 20 12 21 13 22 14 23 15 24 16 25 17 26 18 27 19 28 1A
MSM6562B-xx display
MSM5259 display 14 15 16 17 18 19 1A 1B 1C
(Display shifted to left)
01
02
03
04
13
1-4)
Since the MSM6562B-xx has a DD RAM with a capacity of 80 characters, up to 8 devices of MSM5259 can be connected to MSM6562B-xx so that 80 characters can be displayed.
First digit 2
3
4
19 20 21 22 23 24 25 26 27 28 29 30 12 13 14 15 16 17 18 19 1A 1B 1C 1D MSM5259 (1) display MSM5259 (2)-(7) display
77 78 79 80 4C 4D 4E 4F MSM5259 (8) display
00 01 02 03
MSM6562B-xx display
(Only the half of the segment output pins, i.e., O1 to O20, are used.)
15/50
Semiconductor 2-1)
MSM6562B-xx
Correspondence between address and display position in the 2-line display mode
First digit 2 01 41 3 02 42 4 03 43 5 04 44 39 26 66 40 27 67 Display position DD RAM address (hex.)
First line Second line
00 40
(Note) Note that the last address of the first line and the leading address of the second line are not consecutive.
2-2)
When the MSM6562B-xx alone is used, up to 40 characters (20 character 2 lines) can be displayed from the first digit to the twentieth digit.
First digit 2 01 41 3 02 42 4 03 43 19 12 52 20 13 53
First line Second line
00 40
When the display is shifted by instruction, the correspondence between the LCD display position and the DD RAM address changes as shown below:
First digit First line (Display shifted to right) Second line 27 67 2 00 40 2 02 42 3 01 41 3 03 43 4 02 42 4 04 44 19 11 51 19 13 53 20 12 52 20 14 54
First digit First line (Display shifted to left) Second line 01 41
2-3)
When the MSM6562B-xx is used with one MSM5259, up to 56 characters (28 characters 2 lines) can be displayed from the first digit to the twenty-eighth digit as shown below:
First digit 2 01 41 3 02 42 4 03 43 19 12 52 20 13 53 21 14 54 22 15 55 23 16 56 24 17 57 25 18 58 26 19 59 27 1A 5A 28 1B 5B
First line Second line
00 40
MSM6562B-xx display
MSM5259 display
16/50
Semiconductor
MSM6562B-xx
When the display is shifted by instruction, the correspondence between the LCD display position and the DD RAM address changes as shown below:
(Display shifted to right) First digit First line Second line 27 67 2 00 40 3 01 41 4 02 42 19 11 51 20 12 52 21 13 53 22 14 54 23 15 55 24 16 56 25 17 57 26 18 58 27 19 59 28 1A 5A
MSM6562B-xx display (Display shifted to left) First digit First line Second line 01 41 2 02 42 3 03 43 4 04 44 19 13 53 20 14 54 21 15 55 22 16 56
MSM5259 display
23 17 57
24 18 58
25 19 59
26 1A 5A
27 1B 5B
28 1C 5C
MSM6562B-xx display
MSM5259 display
2-4)
Since the MSM6562B-xx has a DD RAM with a capacity of 80 characters, up to 3 devices of MSM5259 can be connected to the MSM6562B-xx in the 2-line display mode.
First digit 2 3 4 19 20 21 22 23 24 25 26 27 28 29 30 12 13 14 15 16 17 18 19 1A 1B 1C 1D 52 53 54 55 56 57 58 59 5A 5B 5C 5D MSM5259 (1) display
MSM5259 (2) display
37 38 39 40 24 25 26 27 64 65 66 67
00 01 02 03 40 41 42 43
MSM6562B display
MSM5259 (3) display (Only the half of the segment output pins, i.e., O1 to O20, are used.)
6. Character Generator ROM (CG ROM) The CG ROM is used to generate 5 7 dot (160 kinds) character patterns or 5 10 dot (32 kinds) character patterns from an 8-bit DD RAM character code signal. The correspondence of 8-bit character codes to character patterns is shown in Table 2. When the 8-bit character code of the CG ROM is written to the DD RAM, the character pattern of the CG ROM corresponding to the code is displayed on the LCD display position corresponding to the DD RAM address.
17/50
Semiconductor
Lower 4 bits
Upper 4 bits
MSB 0000
0010
0011
0100
0101
0110
0111
1010
1011
1100
1101
1110
1111
Table 2
0000 LSB 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110
CG RAM (1) (2) (3) (4) (5) (6) (7) (8) (1) (2) (3) (4) (5) (9) (7) (8) - . / ( ) * + # $ % & !
0 1 2 3 4 5 6 7 8 9 : ; < = > ?
@ A B C D E F G H I J K L M N O
P Q R S T U V W X Y Z [ ] ^ _
/ a b c d e f n h i j k l m n o
p q r s t u v w x y z { U } AE
a a b e m s r g -1
j
R q Q * W u S p X
Character codes and character patterns of standard code (MSM6562B-01)
x n o /
MSM6562B-xx
18/50
1111
Semiconductor 7. Character Generator RAM (CG RAM)
MSM6562B-xx
The CG RAM is used to display user's original character patterns other than those stored in the CG ROM. The CG RAM has the capacity (64 bytes = 512 bits) to write 8 kinds for 5 7 dots or 4 kinds for 5 10 dots. When displaying character patterns stored in the CG RAM, write 8-bit character codes (00 to 07 or 08 to 0F; hex.) shown on the left in Table 2 to the DD RAM. It is then possible to output the character pattern to the LCD display position corresponding to the DD RAM address. The following is a description on how to write and read character patterns to and from the CG RAM. (1) When the character pattern is 5 7 dots (see Table 3) * Method of writing character pattern into the CG RAM by the CPU : The CG RAM address bits 0 to 2 correspond to the line position of the character pattern. First, set increment or decrement by the CPU, and then input the CG RAM address. After this, write character pattern into the CG RAM through DB0 to DB7 line by line. DB0 to DB7 correspond to the CG RAM data bits 0 to 7 in Table 3. The display of the character pattern is turned on when "H" is set as input data, while it is turned off when "L" is set as the input data. Since the ADC is automatically incremented or decremented by 1 after writing the data to the CG RAM, it is not necessary to set the CG RAM address again. When performing a cursor indication, set to "0" all the input data for the line the CG RAM address bits 0 to 2 of which are all "1". Although the CG RAM data bits 0 ~ 4 are output to the LCD as display data, the CG RAM data bits 5 ~ 7 are not. It is possible, however, to use the CG RAM as a data RAM. * Method of displaying the CG RAM character pattern to the LCD : The CG RAM is selected when high-order 4 bits of the character code are all "L". Since bit 3 of the character code is invalid, the display of "0" in Table 3 is selected by character code "00" or "08" (hex.). When the 8-bit character code of the CG RAM is written to the DD RAM, the character pattern of the CG RAM is displayed on the LCD display position corresponding to the DD RAM address. (DD RAM data bits 0 to 2 correspond to CG RAM address bits 3 to 5.)
19/50
Semiconductor (2) When the character pattern is 5 10 dots (see Table 4).
MSM6562B-xx
* Method of writing character pattern into the CG RAM by the CPU : The CG RAM address bits 0 to 3 correspond to the line position of the character pattern. First, set increment or decrement by the CPU, and then input the CG RAM address. After this, write the character pattern into the CG RAM through DB0 to DB7 line by line. DB0 to DB7 correspond to the CG RAM data bits 0 to 7, in Table 4. The display of the character pattern is turned on when "H" is set as the input data, while it is turned off when "L" is set as the input data. Since the ADC is automatically incremented or decremented by 1 after writing the data to the CG RAM, it is not necessary to set the CG RAM address again. When performing a cursor indication, set to "0" all the input data for the line the CG RAM address bits 0 to 2 are all "1". CG RAM data is displayed on the LCD when the CG RAM data ranges from CG RAM data bits 0 to 4 and the CG RAM addresses (address bits 0 to 3) are "0" to "A" (hex.). Other CG RAM data is not displayed on the LCD (that is, when the CG RAM data ranges from CG RAM data bits 5 to 7 and the CG RAM addresses (address bits 0 to 3) are "B" to "F" (hex.)). It is possible, however, to read such CG RAM data through DB0 to DB7. * Method of displaying the CG RAM character pattern to the LCD : The CG RAM is selected when high-order 4 bits of the character code are all "L". Since bits 0 and 3 of the character code are invalid, the display of "b" in Table 4 is selected by character codes "00", "01", "08" and "09" (hex.). When the 8-bit character code of the CG RAM character code is written to the DD RAM,the character pattern of the CG RAM is displayed on the LCD display position corresponding to the DD RAM address. (DD RAM data bits 1 to 2 correspond to CG RAM address bits 4 to 5.)
20/50
Semiconductor Table 3
Example of the CG RAM data (character pattern) corresponding to the CG RAM addresses when the character pattern is 5 7 dots, and relationship between character patterns and the DD RAM data
CG RAM data (character pattern) 765 43210 MSB LSB XX X 0 1 1 1 1 1 0 0 1 1 1 1 1 1 1 0 1 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 0 0 0 1 0 1 0 0 0 1 0 0 0 0 0 1 0 0 1 0 0 0 1 0 0 0 1 1 1 1 1 0 0 1 0 0 0 0 0 1 0 DD RAM data (character code) 765 43210 MSB LSB
CG RAM address 54 MSB 0 0 3 0 2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
10 LSB 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
0
0
1
1
1
1
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
X : Don't Care
, , , ,
XX X 0 1 0 1 0 1 0 1 XX X 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 1 1 1 1 1 1 1 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
MSM6562B-xx
0
0
0
0
X
0
0
0
0
0
0
0
X
0
0
1
0
0
0
0
X
1
1
1
21/50
Semiconductor Table 4
MSM6562B-xx
Example of the CG RAM data (character pattern) corresponding to the CG RAM addresses when the character pattern is 5 10 dots, and relationship between character patterns and the DD RAM data
CG RAM address CG RAM data (character pattern) 765 43210 MSB LSB XX X 0 0 0 1 1 1 1 1 1 1 0 X 0 0 1 0 1 0 1 0 0 0 0 X 0 0 1 0 1 0 1 0 0 0 0 X 0 0 1 0 1 0 1 0 0 0 0 X DD RAM data (character code) 765 43210 MSB LSB
54 MSB 0 0
3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
10 LSB 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
0
0
0
0
, , , , , , ,
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 1 0 1 0 0 0 0 0 X 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 XX X 0 0 0 1 1 1 0 0 0 0 0 X 0 0 1 0 0 0 1 0 0 1 0 X 0 0 1 0 0 0 1 0 0 1 0 X 0 0 1 0 0 0 1 0 0 1 0 X 0 0 1 1 1 1 1 1 1 0 0 X XX X 0 0 1 0 1 1 0 0 0 0 0 X 0 0 1 1 0 0 1 0 0 0 0 X 0 0 0 0 0 0 1 0 0 0 0 X 0 0 1 1 0 0 1 0 0 0 0 X 0 0 1 0 1 1 0 0 0 0 0 X
0
0
0
0
X
0
0
X
0
0
0
0
X
0
1
X
0
0
0
0
X
1
1
X
X : Don't care
22/50
Semiconductor 8. Cursor and Blink Control Circuit
MSM6562B-xx
This circuit generates the LCD cursor and blink. This circuit is under the control of the CPU program. The display of the cursor or blink on the LCD is made at a position corresponding to the DD RAM address set to the ADC. The figure below shows an example of the cursor and blink position when the value of the ADC is set at "07" (hex.).
DB6 ADC L L 0 L L H 7 H DB0 H
First digit 2 In 1-line display mode 00 01
3 02
4 03
5 04
6 05
7 06
8 07
9 08
79 4E
80 4F
Cursor and blink position
First digit 2 In 2-line display mode First line Second line 00 40 01 41
3 02 42
4 03 43
5 04 44
6 05 45
7 06 46
8 07 47
9 08 48
39 26 66
40 27 67
Cursor and blink position
(Note)
The cursor and blink are displayed even when the CG RAM address is set to the ADC. For this reason, it is necessary to inhibit the display of the cursor and blink while the CG RAM address is set to the ADC.
23/50
Semiconductor
MSM6562B-xx
9. LCD Display Circuit (COM1 to COM16, SEG1 to SEG100, L, CP, DO, DF, SHL0, SHL1) : Since the MSM6562B-xx provides the COM signal outputs (16 outputs) and the SEG signal outputs (100 outputs), even a single MSM6562B-xx device can display 20 characters (1-line display) or 40 characters (2-line display). The character pattern data is converted into the serial data and is serially transferred through the shift register. The transfer direction of the serial data is controlled by SHL0 and SHL1 and is shown as follows.
SHL0 L L H H SHL1 L H L H SEG1AESEG100 SEG100AESEG1 SEG1AESEG50fiSEG100AESEG51 SEG100AESEG1 Transfer direction
Connect SHL0 and SHL1 to VDD or VSS. Keep the set states of the SHL0 and SHL1 pins unchanged during IC operation. The SEG1 to SEG100 are used to display 20-digit display on the LCD. To display more than 20 digits, the character extension IC (MSM5259) is used. The character extension IC (MSM5259) is an extended IC for segment signal output. Interfacing with the MSM5259 is provided through data output pin (DO), clock output pin (CP), latch output pin (L), and display frequency pin (DF). The character pattern data is serially transferred to the MSM5259 through DO and CP. When 60-character (= 1-line display) or 20-character (= 2-line display) is output, the latch pulse is also output through pin L. By this latch pulse, the data transferred serially to the MSM5259 is latched to be used as the display data. The display frequency (DF) signal required when the LCD is displayed is also output from DF pin in synchronization with this latch pulse.
24/50
Semiconductor 10. Built-in Reset Circuit
MSM6562B-xx
The MSM6562B-xx is automatically initialized when the power is turned on. During initialization, the busy flag (BF) holds "H" and does not accept instructions (other than the busy flag read). The busy flag goes to "H" for 15 ms after VDD reaches 4.5V or more. During initialization, the MSM6562B-xx executes the following instructions : * Display clear * Data length of interface with CPU : 8 bits (8B/4B = "H") * LCD : 1-line display (N = "L") * Character font : 5 7 dots (F = "L") * ADC : increment (I/D = "H") * No display shift (S = "L") * Display : Off (D = "L") * Cursor : Off (C = "L") * No blink (B = "L") * Contrast data : 1F (hex.) set When the built-in reset circuit is used, the power supply conditions shown in the figure below must be satisfied. If they are not satisfied, because in that case the built-in reset circuit does not operate normally, initialize the MSM6562B-xx by instruction through the CPU (see the section on instruction initialization). If a battery is used as supply voltage source, be sure to initialize the instruction.
4.5V
0.2V VDD tON
0.2V
0.2V
tOFF
0.1ms tON 100ms
1ms tOFF
Power ON/OFF waveform
25/50
Semiconductor 11. Data Bus with CPU
MSM6562B-xx
The MSM6562B-xx has either a one-step access in 8 bits or a two-step access in 4 bits to execute an instruction so that the MSM6562B-xx can interface with both an 8-bit CPU and a 4-bit CPU. (1) When the interface data length is 8 bits Data buses DB0 to DB7 (8 lines) are all used and data input/output is carried out in one step. (2) When the interface data length is 4 bits The 8-bit data input/output is carried out in two steps by using only high-order 4 bits of data buses DB4 to DB7 (4 lines). The first time data input/output is made for high-order 4 bits (DB4 to DB7 when the interfaces data length is 8 bits) and the second time data input/output is made for loworder 4 bits (DB0 to DB3 when the interface data length is 8 bits). Even when the data input/output can be completely made through high-order 4 bits, be sure to make another input/output of low-order 4 bits. (Example : Busy flag read) Since the data input/output is carried out in two steps but as one execution, no normal data transfer is executed from the next input/output if accessed only once.
26/50
Semiconductor
MSM6562B-xx
RS1 RS0 R/W E Busy (internal operation) DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 IR7 IR6 IR5 IR4 IR3 IR2 IR1 IR0 Busy
No Busy
DR7 DR6 DR5 DR4 DR3 DR2 DR1 DR0
ADC6 ADC5 ADC4 ADC3 ADC2 ADC1 ADC0
Instruction register (IR) write
Busy flag (BF) and address counter (ADC) read
Data register (DR) write
Example of 8-bit data transfer
27/50
Semiconductor
RS1 RS0 R/W E Busy (internal operation) DB7 DB6 DB5 DB4 IR7 IR6 IR5 IR4 IR3 IR2 IR1 IR0 Busy No Busy ADC3 ADC2 ADC1 ADC0 DR7 DR6 DR5 DR4 DR3 DR2 DR1 DR0
ADC6 ADC5 ADC4 Busy flag (BF) and address counter (ADC) read
Instruction register (IR) write
Data register (DR) write
MSM6562B-xx
Example of 4-bit data transfer
28/50
Semiconductor 12. Instruction Code * Instruction code table
Instruction Code RS1 RS0R/WDB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Display clear 1 0 0 0 0 0 0 0 0 0 Description
MSM6562B-xx
Execution Time CP=OSC=250kHz 1.64ms
Cursor home
1
0
0
0
0
0
0
0
0
1
After all display are cleared, 1 address counter for DD RAM is set to "00". Address counter for DD RAM is set to "00". The shifted display returns ] to the position before shift. The contents of the DD RAM are not changed.
1.64ms
Entry mode setting
1
0
0
0
0
0
0
0
Direction of the cursor move and whether display is shifted are set. 1 I/D S Upon data write or read, the cursor and the display will actually be moved and shifted. The on/off of all display (D), the on/off of the cursor (C) and the B blink (B) of the character at the cursor position are set. The cursor and display are ] shifted without changing the contents of the DD RAM. The interface data length (8B/4B), ] the display line numbers (N) and the character font (F) are set. The address of the CG RAM is set and then the CG RAM data is specified for the data for transmission and reception. The address of the DD RAM is set and then the DD RAM data is specified for the data for transmission and reception. The busy flag (BF) indicating that the internal circuits are operating and the contents of address counter are read out. Data is written into the DD RAM or CG RAM Data is read out from the DD RAM or CG RAM. The data for contrast adjustment is written. The data for contrast adjustment is read.
Display data RAM Character generator RAM CG RAM address DD RAM address, corresponding to the cursor address Address counter, used for both DD RAM and CG RAM
40ms
Display on/off control
1
0
0
0
0
0
0
1
D
C
40ms
Cursor/display shift
1
0
0
0
0
0
1 S/C R/L ] 8B/ N 4B
40ms
Function setting
1
0
0
0
0
1
F
]
40ms
CG RAM address setting
1
0
0
0
1
ACG
40ms
DD RAM address setting
1
0
0
1
ADD
40ms
Busy flag/address read
1
0
1
BF
ADC
1ms
CG RAM/DD RAM data write CG RAM/DD RAM data read Contrast adjusting data write Contrast adjusting data read
1
1
0
WRITE DATA
40ms
1
1
1
READ DATA WRITE CONTRAST DATA READ CONTRAST DATA
Decrement
40ms
0
0
0
0
0
1
40ms
0
0
1
0
0
0
40ms
When the frequency is changed, the execution time is also changed. (Example) When CP or OSC=270kHz, 40s 250 = 37s 270 ]: Don't Care
I/D=1 : S=1 : S/C=1 : R/L=1 : 8B/4B=1: N=1 : F=1 : BF=1 :
Increment , I/D=0 : Always involves display shift Shift of display , S/C=0 : Shift to the right , R/L=0 : 8 bits , 8B/4B=0 : 2 lines , N=0 : 510-dots , F=0 : Engaged in , BF=0 : internal operation
DD RAM : CG RAM : Shift of cursor ACG : Shift to the left ADD : 4 bits 1 line 57-dots ADC : Instruction acceptable
29/50
Semiconductor 13. Description of Instructions
MSM6562B-xx
The instruction code is defined as the signal through which the MSM6562B-xx is accessed by the CPU. The MSM6562B-xx begins operation upon receipt of the instruction code input. As the internal processing operation of MSM6562B-xx is started with a timing that does not affect the LCD display, the busy status continues longer than the CPU cycle time. Under the busy status (when the busy flag is set to "H"), the MSM6562B-xx does not execute any instructions other than the busy flag read. Therefore, it must be confirmed before an instruction code is input from the CPU that the busy flag is set to "L". (1) Display clear When this instruction is executed, the LCD display is cleared. The I/D value for the entry mode set instruction is set to 1 (increment). The S value for the entry mode set instruction does not change. When the cursor and blink are being displayed, the blinking and cursor position moves to the left end of the LCD (the left end of the first line in the 2-line display mode).
RS1 Instruction code 1 RS0 0 R/W 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 0 DB2 0 DB1 0 DB0 1
(Note)
All DD RAM data goes to "20" (hex.), while the address counter (ADC) goes to "00" (hex.) of the DD RAM address. The execution time when the OSC oscillation frequency is 250kHz is 1.64ms (max.).
(2) Cursor home When this instruction is executed, the cursor and blinking position move to the left end of the LCD (to the left end of the first line in the 2-line display mode) when the cursor and blink are being displayed. When the display is in shift, the display returns to its original position before shifting.
RS1 Instruction code 1 RS0 0 R/W 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 0 DB2 0 DB1 1 DB0 X
X : Don't Care
(Note)
The address counter (ADC) goes to "00" (hex.) of the DD RAM address. The execution time when the OSC oscillation frequency is 250kHz is 1.64ms (max.).
30/50
Semiconductor (3) Entry mode set
RS1 Instruction code 1 RS0 0 R/W 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 0
MSM6562B-xx
DB2 1
DB1 I/D
DB0 S
1 When the I/D is set, the 8-bit character code is written or read to and from the DD RAM, the cursor and blink shift to the right by 1 character position (I/D = "H"; increment) or to the left by 1 character position (I/D = "L"; decrement). The address counter (ADC) is incremented (I/D = "H") or decremented (I/D = "L") by 1 at this time. Even after the character pattern code is written or read to and from the CG RAM, the address counter (ADC) is incremented (I/D = "H") or decremented (I/ D = "L") by 1. 2 When S = "H" is set, the character code is written to the DD RAM, and then the cursor and blink stop and the entire display shifts to the left (I/D = "H") or to the right (I/D = "L") by 1 character position. When the character is read from the DD RAM when S = "H" is set, or when the character pattern data is written or read to or from the CG RAM when S = "H" is set, the entire display does not shift, but normal write/read is performed (the entire display does not shift, but the cursor and blink shift to the right (I/D = "H") or to the left (I/D = "L") by 1 character position). When S = "L" is set, the display does not shift, but normal write/read is performed. The execution time, when the OSC oscillation frequency is 250kHz, is 40ms.
(4) Display ON/OFF control
RS1 Instruction code 1 RS0 0 R/W 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 1 DB2 D DB1 C DB0 B
1 The D bit controls whether the character pattern is displayed or not. When D is "H", this bit makes the character pattern display on the LCD. When D is "L", this bit makes the display of the character pattern turned off. The cursor and blink are also cancelled at this time. (Note) Different from the display clear, the DD RAM data is absolutely not rewritten.
2 The cursor goes off when C = "L" and it is displayed when D = "H" and C = "H". 3 A blink is cancelled when B = "L" and a blink is executed when D = "H" and B = "H". In the blink mode, all dots (including the cursor) and displaying character pattern (including the cursor) are displayed alternately at 409.6ms (in 5 7 dots character font) or 563.2ms (in 5 10 dots character font) when the OSC oscillation frequency is 250kHz. The execution time, when the OSC oscillation frequency is 250kHz, is 40ms.
31/50
Semiconductor (5) Cursor/display shift
RS1 Instruction code 1 RS0 0 R/W 0 DB7 0 DB6 0 DB5 0 DB4 1 DB3 S/C
MSM6562B-xx
DB2 R/L
DB1 X
DB0 X
X : Don't Care
When S/C = "L" and R/L = "L", the cursor and blink position are shifted to the left by 1 character position (the ADC is then decremented by 1). When S/C = "L" and R/L = "H", the cursor and blink position are shifted to the right by 1 character position (the ADC is then incremented by 1). When S/C = "H" and R/L = "L", the entire display is shifted to the left by 1 character position. The cursor and blink position are also shifted together with the display (ADC remains unchanged). When S/C = "H" and R/L = "H", the entire display is shifted to the right by 1 character position. The cursor and blink position are also shifted together with the display (ADC remains unchanged). In the 2-line display mode, the cursor and blink position are shifted from the first line to the second line when the cursor is shifted to the right next to the fortieth digit (27; hex.) in the first line. No such shifting is made in other cases. When shifting the entire display, the display pattern, cursor and blink position are not shifted between lines (from the first line to the second line or vice versa). The execution time, when the OSC oscillation frequency is 250kHz, is 40ms. (6) Function set
RS1 Instruction code 1 RS0 0 R/W 0 DB7 0 DB6 0 DB5 1 DB4 8B/4B DB3 N DB2 F DB1 X DB0 X
X : Don't Care
1 When 8B/4B = "H", the data input/output to and from the CPU is carried out in one step using 8 bits of DB7 to DB0 . When 8B/4B = "L", the data input/output to and from the CPU is carried out in two steps using 4 bits of DB7 to DB4. 2 The 2-line display mode of the LCD is selected when N = "H", while the 1-line display mode is selected when N = "L". 3 The 5 7 dots character font is slected when F = "L", while the 5 10 dots character font is selected when F = "H" and N = "L". Do this initial setting prior to other instructions except the busy flag read after power is applied to the MSM6562B-xx. After that, no initial setting other than setting of 8B/4B value can be done.
N L L H H F L H L H Number of display lines 1 1 2 2 Character font 5x7 dots 5x10 dots 5x7 dots 5x7 dots Duty ratio 1/8 1/11 1/16 1/16 Number of biases 4 4 5 5 Number of COMMON signals 8 11 16 16
The execution time, when the OSC oscillation frequency is 250kHz, is 40ms 32/50
Semiconductor (7) CG RAM address set
RS1 Instruction code 1 RS0 0 R/W 0 DB7 0 DB6 1 DB5 C5 DB4 C4 DB3 C3
MSM6562B-xx
DB2 C2
DB1 C1
DB0 C0
The CG RAM address is set to a value indicated by C5 to C0 (binary). Once the CG RAM address is set, the CG RAM is specified until the DD RAM address is set. Write/read of the character pattern to and from the CPU begins with the current CG RAM address indicated by C5 to C0. The execution time, when the OSC oscillation frequency is 250kHz, is 40ms. (8) DD RAM address set
RS1 Instruction code 1 RS0 0 R/W 0 DB7 1 DB6 D6 DB5 D5 DB4 D4 DB3 D3 DB2 D2 DB1 D1 DB0 D0
The DD RAM address is set to a value indicated by D6 to D0 (binary). Once the DD RAM address is set, the DD RAM is specified until the CG RAM address is set. Write/read of the character code to and from the CPU begins with the current DD RAM address indicated by D6 to D0. In the 1-line mode (N="L"), D6 to D0 (binary) must be set to one of the values among "00" to "4F" (hex.). Likewise, in the 2-line mode (N="H"), D6 to D0 (binary) must be set to one of the values among "00" to "27" (hex.) or "40" to "67" (hex.). When any value other than the above is input, it is impossible to make a normal write/ read of character codes to and from the DD RAM. The execution time, when the OSC oscillation frequency is 250kHz, is 40ms. (9) DD RAM and CG RAM data write
RS1 Instruction code 1 RS0 1 R/W 0 DB7 E7 DB6 E6 DB5 E5 DB4 E4 DB3 E3 DB2 E2 DB1 E1 DB0 E0
E7 to E0 (binary) codes are written to the DD RAM or CG RAM. Once they are written, the cursor and display move as described in "(5) Cursor/display shift". The execution time, when the OSC oscillation frequency is 250kHz, is 40ms.
33/50
Semiconductor (10) Busy flag and address counter read (execution time = 1ms)
RS1 Instruction code 1 RS0 0 R/W 1 DB7 BF DB6 O6 DB5 O5 DB4 O4 DB3 O3
MSM6562B-xx
DB2 O2
DB1 O1
DB0 O0
The busy flag (BF) is output by this instruction to indicate whether the MSM6562B is engaged in internal operations (BF = "H") or not (BF = "L"). When BF = "H", no new instruction is accepted. It is therefore necessary to confirm BF = "L" before inputting a new instruction. When BF = "L", a correct address counter value is output. The address counter value must match the DD RAM address or CG RAM address. The decision of whether it is a DD RAM address or CG RAM address is made by the address previously set. Since the address counter value when BF = "H" may be incremented or decremented by 1 during internal operations, it is not always a correct value.
(11) DD RAM and CG RAM data read
RS1 Instruction code 1 RS0 1 R/W 1 DB7 P7 DB6 P6 DB5 P5 DB4 P4 DB3 P3 DB2 P2 DB1 P1 DB0 P0
Character codes (P7 to P0) are read from the DD RAM, and character patterns (P7 to P0) are read from the CG RAM. Selection of DD RAM or CG RAM is decided by the address previously set. After reading those data, the address counter (ADC) is incremented or decremented by 1 as set by the shift mode mentioned in item "(3) Entry mode setting". The execution time, when the OSC oscillation frequency is 250kHz, is 40ms. Correct data is read if any of the following conditions are met: 1 When the DD RAM address or CG RAM address setting instruction is input before inputting this instruction. 2 When the cursor/display shift instruction is input before inputting this instruction in cases where case the character code from the DD RAM is read. 3 When reading the data after the second reading from RAM when read more than once. Correct data is not output in any other case. The execution time, when the OSC oscillation frequency is 250kHz, is 40ms. (Note)
34/50
Semiconductor (12) Contrast adjusting data write
RS1 Instruction code 0 RS0 0 R/W 0 DB7 0 DB6 0 DB5 1 DB4 F4 DB3 F3
MSM6562B-xx
DB2 F2
DB1 F1
DB0 F0
The contrast adjusting data (F4 to F0) is written to the contrast register. After writing, the voltage output to V5' is changed according to the data. When the contents of the contrast register are "1F" (hex.), the VLCD becomes maximum. When they are "00" (hex.), it becomes minimum. (The contrast adjusting is valid only when the V5' and V5 pins are connected externally.)
VDD
The voltage between VDD and V5' becomes VLCD.
V5' Pin voltage
V5' Pin voltage
0 1 2 3 4 5 6 7 8 9 A B C D E F 10 11 12 13 14 15 16 17 18 191A1B1C1D1E 1F Contrast Data
The execution time, when the OSC oscillation frequency is 250kHz, is 40ms.
35/50
Semiconductor (13) Contrast adjusting data read
RS1 Instruction code 0 RS0 0 R/W 1 DB7 0 DB6 0 DB5 0 DB4 G4 DB3 G3 DB2 G2
MSM6562B-xx
DB1 G1
DB0 G0
The contents (G4 to G0) of the contrast register are read out. The execution time, when the OSC oscillation frequency is 250kHz, is 40ms.
36/50
Semiconductor 14. Interface with LCD and the Character Extension IC (MSM5259)
MSM6562B-xx
Display examples when setting the 5 7 dots character font 1-line mode (Figure 1), 5 10 dots character font 1-line mode (Figure 2), and 5 7 dots character font 2-line mode (Figs. 3 and 4) through instructions are shown below. When the 5 7 dots character font is set in the 1-line display mode, COM9 to COM16 output the COM signals for turning the display off. Likewise, when the 5 10 dots character font is set in the 1-line display mode, COM12 to COM16 output the COM signals for turning the display off. The display examples show 20 characters (40 characters in Figure 3, 32 characters in Figure 4). When the number of MSM5259s are increased according to the increase in the number of characters, it is possible to display a maximum of 80 characters. The bias voltage required to operate the LCD is made by a bias dividing resistor built in the MSM6562B-xx and this voltage must be input to the MSM5259. These bias examples are shown in Figures 5, 6, 7 and 8 and there are following two ways for adjusting the bias voltage. As shown in Figures 5 and 6, this method divides the bias by installing VR to V5. On the other hand, as shown in Figures 7 and 8, this uses the built-in contrast adjusting circuit by connecting V5 and V5'. Figure 9 shows the connection of the MSM6562B-xx and the MSM5259 including the bias circuit. (The example shows the display of 40 characters and 2 lines using the built-in contrast adjusting circuit.) In addition, the bias voltage must keep the potential relation of VDD > V1 > V2 V3 (= V3') > V4 > V5 VSS.
* In the case of 1-line 20-character display (5 7 dot/font)
COM1
COM8
SEG1
SEG100
DO CP
MSM6562B-xx Figure 1
DF
L
37/50
Semiconductor * In the case of 1-line 20-character display (5 10 dot/font)
MSM6562B-xx
COM1
COM11
SEG1
SEG100
DO CP
MSM6562B-xx Figure 2
DF
L
* In the case of 2-line 20 character display (5 7 dot/font)
COM1
COM8
COM9
COM16
SEG1
SEG100 DO CP MSM6562B-xx Figure 3 DF L
38/50
Semiconductor * In the case of 2-line 16-character display (5 7 dot/font)
MSM6562B-xx
COM1
COM8
COM9
COM16
SEG1
SEG80
SEG100 DO CP
MSM6562B-xx Figure 4
DF
L
39/50
Semiconductor * VLCD variable circuit using external VR (1-line display mode, 1/4 bias)
VDD VDD V1 V2 MSM6562B-xx V3' V3 V4 V5 V5' VR VSS Figure 5 Figure 6 VLCD VDD V1 V2 MSM6562B-xx V3' V3 V4 V5 V5'
MSM6562B-xx * VLCD variable circuit using external VR (2-line display mode, 1/5 bias)
VDD
VLCD
VR VSS
* Internal VLCD variable circuit (1-line display mode, 1/4 bias)
VDD VDD V1 V2 MSM6562B-xx V3' V3 V4 V5 V5' VLCD
* Internal VLCD variable circuit (2-line display mode, 1/5 bias)
VDD VDD V1 V2 MSM6562B-xx V3' V3 V4 V5 V5' VLCD
Figure 7
Figure 8
(VLCD : LCD driving voltage)
40/50
Semiconductor
* Connection between MSM6562B-xx and MSM5259 (40 characters, 2 lines)
LCD
COM1-16
SEG1-100 DO
O1 - O40
O1 - O40
O1 - O20
MSM5259
DI1 CP LOAD DF DO40 DO20 DI21
MSM5259
DI1 CP LOAD DF DO40 DO20 DI21
MSM5259
DI1 CP LOAD DF DO40 DO20 DI21
VDD VSS V2 V3 VEE
VDD VSS V2 V3 VEE
VDD VSS V2 V3 VEE
Figure 9
MSM6562B-xx
CP L DF VDD VSS
V1 V2 V3' V3 V4 V5 V5'
MSM6562B-xx
41/50
+5V
0V
Semiconductor 15. Instruction Initialization
MSM6562B-xx
(1) When data input/output to and from the CPU is carried out by 8 bits (DB0 to DB7) : 1 2 3 4 5 6 7 8 9 * * * * * * * * * Turn on the power. Wait for 15ms or more after VDD has reached 4.5V or more. Set 8B/4B to "H" by the Function setting instruction. Wait for 4.1ms or more. Set 8B/4B to "H" by the Function setting instruction. Wait for 100ms or more. Set 8B/4B to "H" by the Function setting instruction. Check the busy flag as No Busy. Set 8B/4B to "H", the number of lines displayed on LCD (N) and character font (F) by the Function setting instruction. (After this, the number of lines displayed on LCD and character font cannot be changed.) Check No Busy. Display off by the Display on/off control instruction. Check No Busy. Execute the Display clear instruction. Check No Busy. Execute the Entry mode setting instruction. Check No Busy. Initialization completed.
0 A B C D E F G
* * * * * * * *
Example of Instruction Code for Steps 3, 5 and 7.
RS1 1 RS0 0 R/W 0 DB7 0 DB6 0 DB5 1 DB4 1 DB3 X DB2 X DB1 X DB0 X
X : Don't Care
(2) When data input/output to and from the CPU is carried out by 4 bits (DB4 to DB7) : 1 2 3 4 5 6 7 8 9 0 A * * * * * * * * * * * Turn on the power. Wait for 15ms or more after VDD has reached 4.5V or more. Set 8B/4B to "H" by the Function setting instruction. Wait for 4.1ms or more. Set 8B/4B to "H" by the Function setting instruction. Wait for 100ms or more. Set 8B/4B to "H" by the Function setting instruction. Check the busy flag as No Busy (or wait for 100ms or more). Set 8B/4B to "L" by the Function setting instruction. Wait for 100ms or more. Set 8B/4B to "L", the number of lines displayed on LCD (N) and character font (F) by the Function setting instruction. (After this, the number of lines displayed on LCD and character font cannot be changed.)
42/50
Semiconductor B C D E F G H I * * * * * * * * Check No Busy. Display off by the Display on/off control instruction. Check No Busy. Execute the Display clear instruction. Check No Busy. Execute the Entry mode setting instruction. Check No Busy. Initialization completed.
MSM6562B-xx
Example of Instruction Code for Steps 3, 5 and 7.
RS1 1 RS0 0 R/W 0 DB7 0 DB6 0 DB5 1 DB4 1
Example of Instruction Code for Step 8.
RS1 1 RS0 0 R/W 1 DB7 BF DB6 O6 DB5 O5 DB4 O4
Example of Instruction Code for Step 9.
RS1 1 RS0 0 R/W 0 DB7 0 DB6 0 DB5 1 DB4 0
Execute steps A to H with two-step accesses in 4 bits.
43/50
Semiconductor 16. LCD Driving Waveforms
MSM6562B-xx
Figures 10, 11 and 12 show the LCD driving waveforms that consist of COM waveforms, SEG waveform, DF (display frequency) signal and L (latch pulse) signal, in the duty of 1/8, 1/11 and 1/16 respectively. The relation between duty and frame frequency is as follows:
Duty 1/8 1/11 1/16 Frame frequency 78.1Hz 56.8Hz 78.1Hz
(Note)
The OSC oscillation frequency is assumed to be 250kHz.
44/50
Semiconductor
MSM6562B-xx
78123456781234567812 VDD V1 V2,V3 V4 V5 1 frame VDD V1 V2,V3 V4 V5
COM1
COM2
COM8
VDD V1 V2,V3 V4 V5
COM9
VDD V1 V2,V3 V4 V5
COM16
VDD V1 V2,V3 V4 V5 Display turning-off waveform VDD V1 V2,V3 V4 V5
SEG (Output example)
Display turning-on waveform
DF
L
Figure 10 LCD driving waveforms at 1/8 duty
45/50
Semiconductor
MSM6562B-xx
10 11 1 2 3 4 5 6 7 8 9 10 11 1 2 3 4 5 VDD V1 V2,V3 V4 V5 1 frame VDD V1 V2,V3 V4 V5
COM1
COM2
COM11
VDD V1 V2,V3 V4 V5
COM12
VDD V1 V2,V3 V4 V5
COM16
VDD V1 V2,V3 V4 V5 Display turning-off waveform VDD V1 V2,V3 V4 V5 Display turning-on waveform DF
SEG (Output example)
L
Figure 11 LCD driving waveforms at 1/11 duty
46/50
Semiconductor
MSM6562B-xx
15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 VDD V1 V2 V3 V4 V5 1 frame VDD V1 V2 V3 V4 V5
COM1
COM2
COM16
VDD V1 V2 V3 V4 V5
Display turning-off waveform
SEG (Output example)
VDD V1 V2 V3 V4 V5
Display turning-on waveform
DF
L
Figure 12 LCD driving waveforms at 1/16 duty
47/50
Semiconductor
MSM6562B-xx
PAD CONFIGURATION Pad Layout
Chip Size : 7.12 4.09 mm Pad Size : 100 100 mm (PV Hole) 210 100 mm (VDD, VSS) Chip Thickness : 525 20 mm
122 123 Y
76 75
X
149 1 47
48
Note :
The chip substrate should be connected to VDD or left open.
Pad Coordinates
Pad 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Symbol T2 T3 VSS COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 SEG100 X (m) -3275 -3135 -2940 -2745 -2605 -2465 -2325 -2185 -2045 -1905 -1765 -1625 -1485 -1345 -1205 -1065 -925 -785 -645 -505 Y (m) -1900 -1900 -1900 -1900 -1900 -1900 -1900 -1900 -1900 -1900 -1900 -1900 -1900 -1900 -1900 -1900 -1900 -1900 -1900 -1900 Pad 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Symbol SEG99 SEG98 SEG97 SEG96 SEG95 SEG94 SEG93 SEG92 SEG91 SEG90 SEG89 SEG88 SEG87 SEG86 SEG85 SEG84 SEG83 SEG82 SEG81 SEG80 X (m) -365 -225 -85 55 195 335 475 615 755 895 1035 1175 1315 1455 1595 1735 1875 2015 2155 2295 Y (m) -1900 -1900 -1900 -1900 -1900 -1900 -1900 -1900 -1900 -1900 -1900 -1900 -1900 -1900 -1900 -1900 -1900 -1900 -1900 -1900
48/50
Semiconductor
MSM6562B-xx
Pad Coordinates (continued)
Pad 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 Symbol SEG79 SEG78 SEG77 SEG76 SEG75 SEG74 SEG73 SEG72 SEG71 SEG70 SEG69 SEG68 SEG67 SEG66 SEG65 SEG64 SEG63 SEG62 SEG61 SEG60 SEG59 SEG58 SEG57 SEG56 SEG55 SEG54 SEG53 SEG52 SEG51 SEG50 SEG49 SEG48 SEG47 SEG46 SEG45 SEG44 SEG43 SEG42 SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 X (m) 2435 2527 2715 2855 2995 3135 3275 3415 3415 3415 3415 3415 3415 3415 3415 3415 3415 3415 3415 3415 3415 3415 3415 3415 3415 3415 3415 3415 3415 3415 3415 3415 3415 3415 3415 3275 3135 2995 2855 2715 2575 2435 2295 2155 2015 Y (m) -1900 -1900 -1900 -1900 -1900 -1900 -1900 -1900 -1750 -1610 -1470 -1330 -1190 -1050 -910 -770 -630 -490 -350 -210 -70 70 210 350 490 630 770 910 1050 1190 1330 1470 1610 1750 1900 1900 1900 1900 1900 1900 1900 1900 1900 1900 1900 Pad 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 Symbol SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 VDD SHL0 SHL1 OSC1 OSCR OSC2 V1 V2 V3' V3 V4 X (m) 1875 1735 1595 1455 1315 1175 1035 895 755 615 475 335 195 55 -85 -225 -365 -505 -645 -785 -925 -1065 -1205 -1345 -1485 -1625 -1765 -1905 -2045 -2185 -2325 -2465 -2605 -2745 -2940 -3135 -3275 -3415 -3415 -3415 -3415 -3415 -3415 -3415 -3415 Y (m) 1900 1900 1900 1900 1900 1900 1900 1900 1900 1900 1900 1900 1900 1900 1900 1900 1900 1900 1900 1900 1900 1900 1900 1900 1900 1900 1900 1900 1900 1900 1900 1900 1900 1900 1900 1900 1900 1820 1680 1540 1400 1260 1120 980 840
49/50
Semiconductor
MSM6562B-xx
Pad Coordinates (continued)
Pad 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 Symbol V5 V5' L CP DF DO RS0 RS1 R/W E DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 T1 X (m) -3415 -3415 -3415 -3415 -3415 -3415 -3415 -3415 -3415 -3415 -3415 -3415 -3415 -3415 -3415 -3415 -3415 -3415 -3415 Y (m) 700 560 420 280 140 0 -140 -280 -420 -560 -700 -840 -980 -1120 -1260 -1400 -1540 -1680 -1820 Pad Symbol X (m) Y (m)
50/50

▲Up To Search▲

Price & Availability of MSM6562B

	To Download MSM6562B Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .